A) Technical Field
The present invention relates to methods of generating a multi-pattern signal for testing of an integrated circuit featuring scan design, and to measurement of a signal in such an integrated circuit as well as to a test system for testing of such an integrated circuit.
B) Background Art
One of the best known test methods for testing large scale integrated circuits is level sensitive scan design (LSSD), which is generally described in the article "A Logic Design Structure for LSI Testability", Proceedings of the Design Automation Conference, No. 14, 20-22, Jun. 1977, New Orleans, La., by E. B. Eichelberger. See also U.S. Pat. No. 4,590,078 and U.S. Pat. No. 4,428,060. See an article by E. J. McCluskey, "A Survey of Design for Testability Scan Techniques", VLSI Design, December 1984, pp. 38-61, for a comprehensive list of patents and publications for the testing of electronic structures.
Basically, LSSD utilizes a plurality of controllability/observability points internal to an LSI circuit. Controllability is provided by allowing data to be shifted into these points which are comprised of shift register latches (SRL's) in a serial manner. A test is then performed. The resulting data stored in the SRL's is subsequently shifted back out for observation thereof. Therefore, control/observation of an LSI circuit does not depend on the number of pins in the package. Furthermore, because the latches themselves are part of the internal circuit, they can be utilized to break feed-back paths in a sequential circuit, enabling the test for combinational circuits between SRL's to be generated automatically.
In a typical scan design, the shift registers are located at specific points required for the design function but are connected together in the scan chain for testing purposes. The scan chain allows for realization of any test states in the registers for test application. A test pattern is then generated on a computer. The generated test pattern is then shifted into the SRL's; test vectors (selected words or groups of digital data) are applied to the primary inputs or pins of the chip; the system clocks are applied to perform the test, and the signals at the primary output pins are compared to expected vector outputs and data scanned out of the SRL's to compare it to known good test vectors. In performing this test, numerous series of test vectors are usually required for shifting data into the SRL's, applying the test vectors, and then shifting the results back out. In order to fully realize the potential of LSSD testing, test generation software must be able to generate the required test patterns for loading into the SRL's inside the chip.
Another class of scan designs is the boundary scan architecture as defined e.g. in IEEE Std 1149.1. An overview of diverse boundary-scan designs as well as a list of further references is given in "The Test Access Port and Boundary-Scan Architecture", by C. M. Maunder and R. E. Tulloss, IEEE Computer Society Press, Los Alamitos, Calif., 1990.
A common disadvantage of the above described scan-path architectures is that for each test a separate test pattern is shifted into the scan-path. After a functional step is performed the resulting data is shifted out for observation thereof. One example of generating a test pattern is described in U.S. patent application Ser. No. 07/744,760 filed on Aug. 14, 1991 (abandoned). If the scan-path comprises a large number of SRL's and if a large number of test patterns is to be shifted into the scan-path, testing consequently takes a relatively long period of time.